Manufacturers in the electronic industry use test systems to automatically test various electronic components and integrated circuits (ICs) to weed out defective devices or ICs. Generally, it is desirable to test the ICs at several points during the manufacturing process including while they are still part of a wafer or substrate and after packaging the devices before they are mounted or assembled on modules, cards or boards.
Conventional methods for testing devices in the front end (FE), that is before assembly and packaging, are commonly referred to as FE tests and use a low-end, slow tester and a probe card to electrically couple to devices under test (DUTs) in an undiced wafer. Although this approach has the advantages of using a relatively inexpensive tester and of weeding out defective devices prior to incurring the expense of assembly and packaging, it is limited in that these testers can only perform functional tests at low speed and parametric tests.
Because of the limitations of conventional FE testing, it is generally necessary to perform additional back end (BE) tests following assembly and packaging using an expensive, fast high-end tester. These high-end testers, commonly referred to as “big iron” testers, are capable of performing both high speed functional tests and parametric tests. For example, full speed datasheet tests are typically performed in the back end on Big Iron testers.
Conventional BE testing methods have not been wholly satisfactory for a number of reasons. First, the trend in the electronic industry has been to further increase the miniaturization of electronic devices and circuits, thereby leading to an increase in the complexity of the ICs tested. Thus, as ICs become more complex, the complexity and cost of these Big Iron back end testers has increased correspondingly. Moreover, because BE testing is performed only after assembly and packaging, money is wasted on packing “bad” devices, significantly reducing the cost efficiency of the manufacturing process. Attempts have been made at reducing the money wasted on packing defective devices by moving speed tests from the back end to the front end by testing at the wafer level, that is while the devices or ICs are still part of an undiced wafer, using slow, inexpensive testers with an “offset” introduced to compensate for the difference in speed. However, this approach results in the culling of “good” devices at wafer level, leading to yield overkill and again reduces the cost efficiency of the manufacturing process. Moreover, due to setup and hold times on faster synchronous devices even this technique cannot enable full speed datasheet testing using the slower, inexpensive testers typically used in the front end.
Accordingly, there is a need for an apparatus and method for high-speed testing of devices and ICs at the wafer level in the front end. There is a further need for an apparatus and method that enables high-speed, datasheet testing of assembled and packaged devices and ICs in the back end, which eliminates the need for complex and expensive testers.
The present invention provides a solution to these and other problems, and offers further advantages over conventional testing apparatus and methods.